搜索资源列表
full_adder_code_in_verilog
- full adder in verilog
DDS1
- 直接数字频率合成器（Direct Digital synthesizer）是从相位概念出发直接合成所需波形的一种频率合成技术。一个直接数字频率合成器由相位累加器、加法器、波形存储ROM、D/A转换器和低通滤波器（LPF）构成-Direct digital frequency synthesizer (Direct Digital synthesizer) is the concept of direct synthesis from the requirements phase of a wav
Mini_Proj3
- Embedded 16 bit adder designed and implemented on Altera FPGA DE1 board using SOPC system builder and tested with NIO2 software. Language:Verilog and C
ser_adder
- 串入串出加法器 verilog 代码 串入串出加法器 verilog 代码-serial adder verilog code serial adder verilog code
Verilog
- 基于Verilog语言的循环式加法器的设计,是中国科技大学电子与科学系论文-Cycle adder design based on Verilog language, University of Science and Technology of China Electronic Science thesis
carrylook4bit
- carry 4-bit adder program in verilog
21-bit--leading-adder-Verilog
- 这是一个21位超前进位加法器的verilog程序。-21 bit leading adder verilog program.
8-grade-4-pipeline-adder-Verilog
- 这是一个8位4级流水线的加法器的Verilog程序。-This is a eight grade 4 pipeline adder the Verilog program.
16-leading-adder-Verilog-program
- 这是一个16位超前进位加法器的Verilog程序。-This is a 16 bit leading adder verilog program.
xjwbwd
- 这个fpadd程序应用verilog语言，实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look.
ripplecarryadder
- ripple carry adder in verilog
twoBitAdder
- N-bit adder implemented in verilog
fpaddmisc-(1)
- VERILOG CODE FOR FLOating point adder
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
mixed-language--desvription-of-a-4x4-comparator.z
- mixed language (i.e VHDL and verilog ) is used to compute 4x4 comparator.. vhdl full adder is imported to verilog main module.
carrylookaheadadder_4bit
- 4-Bit Carry Look Ahead Adder Verilog Code in Xilinx
Lab1_Skeleton.tar
- adder verilog lab 1 assignment